system verilog - UVM- run test() in top block and Macros -

i'm reading following guide: https://colorlesscube.com/uvm-guide-for-beginners/chapter-3-top-block/

in code 3.2 line 24- run_test(); realized supposed execute test, how know test, , how, , why should write in top block.

in code 4.1 lines 11-14 (https://colorlesscube.com/uvm-guide-for-beginners/chapter-4-transactions-sequences-and-sequencers/):

`uvm_object_utils_begin(simpleadder_transaction) `uvm_field_int(ina, uvm_all_on) `uvm_field_int(inb, uvm_all_on) `uvm_field_int(out, uvm_all_on) `uvm_object_utils_end 

why should add "uvm_field_int" , happend if didn't add them, , "uvm_all_on"?

run_test helper global function , calls run_test function of uvm_root class run test case. there 2 ways can pass test name function.the first via function argument , second via command line argument. command line argument takes precedence on test name passed via function argument.

  +uvm_testname=your_test_name    run_test("your_test_name"); 

run_test function in uvm_root uses factory mechanism create appropriate instance of umm_test class , test case must register factory using macro `uvm_component_utils factory mechanism (create_component_by_name) function.

class your_test_name extends umm_test ;   // register class factory   // run_test can find class when   // string test_name passed it.  `uvm_component_utils(your_test_name) ..... endclass 

the run_test function kicks of uvm_phases (..,build_phase,connect_phase,...) starting uvm portion of simulation. there should no time ticks consumed before run_phase starts , essential run_test case called in initial block itself. want uvm , test bench ready drive , receive data rtl ready essential start run_test @ earliest. delay in doing generate error.

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`uvm_field_int/uvm_field_object/.. called field automation macros. not mandatory in class definition , provided helper macros ease use of many common/routine functions of uvm_object. examples of thse functions in uvm_object - copy,compare,pack,unpack,print, etc , these macros generate code automatically use these functions.

if not using uvm_object common functions leaving out these macros class definition not produce errors. in case implement own version of common operations can leave out these macros class.

uvm_all_on - enables functions compare/copy/... implemented particular field.

link examples - http://www.testbench.in/ut_04_uvm_transaction.html

for example uvm_object has compare function compare 2 instances of same class , return true if variables in class equal.

    virtual function bit do_compare( uvm_object rhs, uvm_comparer comparer );         .....       // return 1 if variables match       return ( super.do_compare( rhs, comparer )  &&                this.var_1    == rhs.var_1           &&                this.var_2    == rhs.var_2          &&                ......                this.var_n      == rhs.var_n );    endfunction: do_compare               // use in main code             if ( new_class.compare(old_classs) )             ...             //instead of             if ( new_class.var1 == old_class.var1 && new_class.var2 == old_class.var2 && ... new_class.varn == old_class.varn )          ... 

the above compare has written each class , updated , maintained every new variable added class. become error prone newer variables added. similar process has followed standard functions uvm_object provides.

the field automation macro generates function address these functionality automatically. doing do_print class macros print out fields without explicitly writing code it.

// compare/print/.. functions class simpleadder_transaction provided using `uvm_field_int  macro. `uvm_object_utils_begin(simpleadder_transaction) `uvm_field_int(ina, uvm_all_on) `uvm_object_utils_end 

but word of caution , use of these macros discouraged add significant amount of code class.. of these functions may not needed class yet generated default.